1. Field of the Invention
The present invention relates to integrated circuit fabrication, and in particular to semiconductor devices capable of sustaining high-voltage and methods for fabricating the same
2. Description of the Related Art
In current integrated circuit processing, controllers, memories, operation of low-voltage circuits and high-voltage (HV) power devices are largely integrated into a single chip, thus achieving a single-chip system. To handle high voltage and current, DMOS (double-diffused metal oxide semiconductor) transistors are conventionally used for the power devices, which can operate with low on-resistance while sustaining high voltage.
LDMOS (lateral double-diffused metal oxide semiconductor) transistors in particular have a simple structure suitable for incorporation into the VLSI logic circuits, however, they have been considered inferior to VDMOS (vertically double-diffused metal oxide semiconductor) transistors as they have high on-resistance. Recently, RESURF (reduced surface field) LDMOS devices, capable of providing low on-resistance, have been introduced and are increasingly used in power devices.
FIG. 1 illustrates a portion of a conventional LDMOS transistor, including a substrate 100, a well region 102, a first oxide region 104, a second oxide region 106, a gate oxide layer 108, a gate electrode 110, a channel well region 112, a source region 114, and a drain region 116.
As shown in FIG. 1, the second oxide region 106 is formed over the substrate 100 and the gate electrode 110 partially covers a portion of the second oxide region 106, therefore enabling high-voltage (HV) operation of the LDMOS transistor. Nevertheless, one problem of the conventional LDMOS transistor of FIG. 1 is that the second oxide region 106 interrupts current flowing from the source region 114 to the drain region 116. This eventually increases on-resistance of the LDMOS transistor.
Moreover, a semiconductor device having the conventional LDMOS transistor of FIG. 1 needs a large cell pitch and is therefore disadvantageous when the size of the semiconductor device is reduced.